Clock gating is a widely used power reduction mechanism in commercial application specific integrated circuits (ASICs). By turning off sections of the clock tree, the switching power (due to capacitances on the clock tree) can be brought to zero. A network on chip (NoC) interconnect offers unique opportunities and challenges while clock gating. Unlike a bus-based interconnect, some discrete components of the NoC can remain gated off while others are on depending on traffic patterns. Additionally, resources on a traffic path can remain off until data flits reach the nodes of the path (“just-in-time gating on”). This leads to much greater power savings. However, frequent gating of components and just-in-time gating on usually leads to increased latency (up to 4-8 cycles per gating on operation at each node) and performance issues. As NoCs usually have greater latency than a traditional bus, additional latency due to aggressive clock gating would not be well tolerated in high performance latency critical implementations. Thus, the full power savings of clock gating cannot be realized in conventional NoC systems.